1. Field of the Invention
This invention relates generally to the structure and fabrication process of MOSFET power devices. More particularly, this invention relates to a new method of manufacturing the MOSFET device to reduce the width of polysilicon gates without increasing the JFET resistance, and also a higher switching speed is achieved with reduced gate-source capacitance. Meanwhile, a shallower source junction is formed in this novel device such that the device ruggedness is improved, a high breakdown voltage is maintained and an early punch through is also prevented.
2. Description of the Prior Art
Conventional structure and processing steps for fabricating a power metal oxide silicon field effect transistor (MOSFET) power device are limited by several technical difficulties. Specifically, conventional planar cellular structure of power MOSFETs, such as square, circular, and hexagonal topologies are limited by the difficulty that the on-resistance is decreased when the polysilicon space is reduced to achieve higher cell density by shrinking unit cell areas. However, a planar DMOS is limited by the surface area occupied by the polysilicon gate electrode. Additional reduction in the size of the gate electrode exacerbate the parasitic JFET pinching effect, leading to higher device on-resistance at a small cell pitch. Conversely, if the polysilicon gate dimension is held constant to avoid the pinching effect, and the size of the source/body region, i.e., the opening in the polysilicon, is reduced instead, the specific on-resistance still increases at high cell densities. This is caused by the transistor gate width per unit area decreases. With such electrical and geometric restrictions, the cell density is limited to 6.5 million cells/inch.sup.2. For a person of ordinary skill in the art, further increases in planar DMOS cell density is unwarranted and likely to be detrimental to performance. The pinching effect caused by cell pitch reduction has to be eliminated to significantly benefit power MOSFET specific on-resistance. Additionally, the JFET resistance can be reduced with a shallower body junction. However, the breakdown voltage of the device is degraded with shallower body junctions. The tradeoffs of these performance characteristics become designer's dilemmas which cannot be easily resolved with conventional planar structures and current state of the art manufacturing technology.
FIG. 1 shows a typical vertical double diffused MOS (VDMOS) device which uses a double diffusion technique to control the channel length L. Two successive diffusions are performed with first a p diffusion using boron, then an N diffusion using either arsenic or phosphorus, to produce two closely spaced pn junctions at different depths below the silicon surface. With this pn-junction, as shown in FIG. 1, the VDMOS supports the drain voltage vertically in the N-epitaxial layer. The current flows laterally from the source through the channel, parallel to the surface of the silicon. The current flow then turns through a right angle to flow vertically down through the drain epitaxial layer to the substrate and to the drain contact. The p-type "body" region in which the channel is formed when a sufficient positive voltage is applied, and the n+ source contact regions are diffused successively through the same window etched in the oxide layer. The channel length can be controlled through the processing steps. Because of the relative doping concentrations in the diffused p-channel region and the N-layer, the depletion layer which supports BVdS, a drain to source voltage, extends down into the epitaxial layer rather than laterally into the channel.
As discussed above, when the width of the gates is reduced to increase the cell density, the body regions are pulled together. The JFET regions between the body regions are pinched and resulting in a higher JFET resistance, i.e., a higher R-JFET. Typically, for a body dopant such as boron, there is a ratio of lateral diffusion to vertical of approximately 0.8. Therefore, if the depth of the body is b, generally the body regions extend lateral from the edges of the gate with a distance of about 0.8b into a region under the gate. Referring to FIG. 2, where a conventional MOSFET device is shown with the body regions formed by implanting the body dopant ions, which are blocked by the polysilicon gates. The body regions are then formed by carrying out a body diffusion. The body regions as shown have a depth of b and a lateral diffusion length .lambda. of 0.8b measured from the edges of the gate. If the width of the gate is G, then the distance J between the body regions is approximately: EQU J=G-2.lambda.=G-2(0.8b) (1)
As the width of the gate G is reduced, the distance J between the body regions is also reduced which causes the JFET resistance to increase. It appears, from Equation (1), that a longer distance of J may be maintained by keep a shallow P-body with reduced value of b. However, a shallow body would create several problems, e.g., device punch through, lower breakdown voltage and reduced device ruggedness. For these reasons, in a conventional MOSFET power device, it is difficult to maintain a same JFET resistance when the cell size is reduced.
Therefore, a need still exists in the art of power device fabrication, particularly for MOSFET design and fabrication, to provide a structure and fabrication process that would resolve these difficulties.